Recently, a method has been used in which an LSI is designed by connecting circuit blocks called as IP cores (Intellectual Property Cores). In order to control each IP core, an IP core control register placed in the each IP core is accessed by a CPU. At this moment, in a case where a plurality of IP cores performing similar processing is used, it is usual that a same value is written to each of the control registers controlling the respective IP cores. However, the CPU must access every control register one by one to write the same value, resulting in a problem the CPU's load increases. In order to solve the problem described above, an LSI is proposed (for example, in Patent Document 1) in which two IP cores are parallelly operated by accessing a common address corresponding to the two IP cores, reducing the CPU's load.